65 lines
2.6 KiB
C
65 lines
2.6 KiB
C
/* SPDX-License-Identifier: AGPL-3.0-or-later */
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/* Copyright (C) 2026 David (Corey) Herrera */
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/**
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* @file ft_tt_phase2_l1_layout.c
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* @brief Derivation of the Phase 2 test L1 map from where the firmware images landed.
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*
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* @status Used by the on-card Phase 2 tests; the arithmetic is unit-tested in
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* tests/test_launch.c, which needs no device.
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* @issues None
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* @todo None
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*/
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#include "ft_tt_phase2_l1_layout.h"
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#include <string.h>
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/** Highest offset any field of the map reaches, plus the two tiles the destination
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* buffer holds. Used to prove a derived base still leaves the map inside L1. */
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#define FT_TT_PHASE2_LAYOUT_SPAN_BYTES \
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(FT_TT_PHASE2_DESTINATION_OFFSET + 2u * FT_TT_PHASE2_TILE_BYTES)
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int ft_tt_phase2_l1_layout_derive(const ft_tt_image_placement *placements, unsigned count,
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ft_tt_phase2_l1_layout *out_layout)
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{
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uint32_t base;
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if (!out_layout)
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return FT_TT_EINVAL;
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memset(out_layout, 0, sizeof(*out_layout));
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base = ft_tt_image_placement_l1_floor(placements, count);
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if (base == 0u)
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return FT_TT_EINVAL;
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if (base < FT_TT_PHASE2_RESERVED_L1_END)
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base = FT_TT_PHASE2_RESERVED_L1_END;
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base = (base + (FT_TT_PHASE2_LAYOUT_ALIGNMENT - 1u)) & ~(FT_TT_PHASE2_LAYOUT_ALIGNMENT - 1u);
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if (base > FT_TT_MEM_L1_SIZE - FT_TT_PHASE2_LAYOUT_SPAN_BYTES) {
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ft_tt_log_error("phase2 layout: base 0x%05x plus a %u byte map does not fit L1", base,
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(unsigned)FT_TT_PHASE2_LAYOUT_SPAN_BYTES);
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return FT_TT_EINVAL;
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}
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out_layout->kernel_config_base = base;
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out_layout->cb_config_address = base + FT_TT_PHASE2_CB_CONFIG_OFFSET;
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out_layout->runtime_args_base = base + FT_TT_PHASE2_RTA_OFFSET;
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out_layout->probe_address = base + FT_TT_PHASE2_PROBE_OFFSET;
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out_layout->cb_in0_address = base + FT_TT_PHASE2_CB_IN0_OFFSET;
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out_layout->cb_in1_address = base + FT_TT_PHASE2_CB_IN1_OFFSET;
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out_layout->cb_out_address = base + FT_TT_PHASE2_CB_OUT_OFFSET;
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out_layout->source0_address = base + FT_TT_PHASE2_SOURCE0_OFFSET;
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out_layout->source1_address = base + FT_TT_PHASE2_SOURCE1_OFFSET;
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out_layout->destination_address = base + FT_TT_PHASE2_DESTINATION_OFFSET;
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out_layout->allocation_floor = base;
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return FT_TT_OK;
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}
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uint32_t ft_tt_phase2_runtime_args_address(const ft_tt_phase2_l1_layout *layout,
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unsigned processor)
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{
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if (!layout || processor >= FT_TT_PROC_COUNT)
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return 0u;
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return layout->runtime_args_base + (uint32_t)processor * FT_TT_PHASE2_RTA_STRIDE;
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}
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