83 lines
3.2 KiB
C
83 lines
3.2 KiB
C
/* SPDX-License-Identifier: AGPL-3.0-or-later */
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/* Copyright (C) 2026 David (Corey) Herrera */
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/**
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* @file ft_tt_tile_row0.c
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* @brief Implementation of the row-0-only tile transfers (see ft_tt_tile_row0.h).
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*
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* @status ON THE CARD — see ft_tt_tile_row0.h for the numbers and the mutation table.
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* @issues None
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* @todo None
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*/
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#include "ft_tt_tile_row0.h"
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#include <string.h>
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uint32_t ft_tt_tile_row0_chunk_offset(uint32_t tile_index, uint32_t chunk)
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{
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/* Chunk 0 is columns 0-15, which live at the START of face 0; chunk 1 is columns
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* 16-31, which live at the start of face 1, one whole face further in. Both facts
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* come from ft_tt_tilize.h's face ordering; a stride of 256 here (half a face, which
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* is what the FACE-INDEX arithmetic uses in ELEMENTS) reads the middle of face 0 and
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* returns a plausible wrong answer with no error anywhere. */
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return tile_index * FT_TT_TILE_ROW0_TILE_BYTES + chunk * FT_TT_TILE_ROW0_FACE_BYTES;
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}
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int ft_tt_tile_row0_read(const ft_tt_noc_access *noc, uint16_t x, uint16_t y,
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uint32_t base_address, uint32_t tile_count, uint16_t *out_row)
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{
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/* One 64 B chunk at a time: the DRAM read alignment, of which the leading 32 B are
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* row 0. Reading the two chunks into one 128 B buffer would not help — they are
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* 512 B apart, so they are two transactions either way. */
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unsigned char chunk_bytes[FT_TT_TILE_ROW0_READ_BYTES];
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uint32_t tile;
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if (!noc || !noc->read || !out_row)
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return FT_TT_EINVAL;
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for (tile = 0; tile < tile_count; tile++) {
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uint32_t chunk;
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for (chunk = 0; chunk < FT_TT_TILE_ROW0_CHUNKS; chunk++) {
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uint32_t offset = ft_tt_tile_row0_chunk_offset(tile, chunk);
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int rc = noc->read(noc->user, x, y, (uint64_t)base_address + offset, chunk_bytes,
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sizeof(chunk_bytes));
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if (rc != FT_TT_OK)
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return rc;
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memcpy(out_row + (size_t)tile * (FT_TT_TILE_ROW0_CHUNKS * FT_TT_TILE_ROW0_HALF_ELEMS) +
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(size_t)chunk * FT_TT_TILE_ROW0_HALF_ELEMS,
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chunk_bytes, FT_TT_TILE_ROW0_HALF_BYTES);
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}
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}
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return FT_TT_OK;
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}
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int ft_tt_tile_row0_write(const ft_tt_noc_access *noc, uint16_t x, uint16_t y,
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uint32_t base_address, uint32_t tile_count, const uint16_t *row)
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{
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uint32_t tile;
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if (!noc || !noc->write || !row)
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return FT_TT_EINVAL;
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for (tile = 0; tile < tile_count; tile++) {
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uint32_t chunk;
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for (chunk = 0; chunk < FT_TT_TILE_ROW0_CHUNKS; chunk++) {
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uint32_t offset = ft_tt_tile_row0_chunk_offset(tile, chunk);
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const uint16_t *source =
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row + (size_t)tile * (FT_TT_TILE_ROW0_CHUNKS * FT_TT_TILE_ROW0_HALF_ELEMS) +
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(size_t)chunk * FT_TT_TILE_ROW0_HALF_ELEMS;
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/* 32 B, not 64: the DRAM WRITE alignment is 16 B, so this direction moves
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* exactly row 0 and nothing else. */
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int rc = noc->write(noc->user, x, y, (uint64_t)base_address + offset, source,
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FT_TT_TILE_ROW0_HALF_BYTES);
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if (rc != FT_TT_OK)
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return rc;
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}
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}
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return FT_TT_OK;
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}
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