150 lines
4.4 KiB
C
150 lines
4.4 KiB
C
/* SPDX-License-Identifier: AGPL-3.0-or-later */
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/* Copyright (C) 2026 David (Corey) Herrera */
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/*
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* mmio_probe.c — Quick MMIO accessibility test for a single die.
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*
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* Acquires a die via bar_swap ioctl, then reads NV_PMC_BOOT_0 (offset 0x0)
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* from BAR 0 via /dev/mem. If we get 0xFFFFFFFF, the die is unreachable.
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* A GK210 should return something like 0x0E0000A1.
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*
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* Usage: sudo ./mmio_probe <die_id>
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include <stdint.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include "../bar_swap_ko/bar_swap.h"
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int main(int argc, char **argv)
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{
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int die_id, fd, mem_fd;
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struct bs_acquire_req acq;
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struct bs_release_req rel;
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void *mapped;
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volatile uint32_t *reg;
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uint32_t boot0, pmc_id;
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if (argc < 2) {
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fprintf(stderr, "usage: %s <die_id>\n", argv[0]);
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return 1;
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}
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die_id = atoi(argv[1]);
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fd = open("/dev/bar_swap", O_RDWR);
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if (fd < 0) {
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perror("open /dev/bar_swap");
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return 1;
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}
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/* Acquire the die */
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memset(&acq, 0, sizeof(acq));
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acq.die_id = die_id;
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if (ioctl(fd, BAR_SWAP_ACQUIRE, &acq) < 0) {
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perror("ACQUIRE ioctl");
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close(fd);
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return 1;
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}
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printf("Die %d acquired: BAR0=0x%llx BAR1=0x%llx BAR3=0x%llx\n",
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die_id,
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(unsigned long long)acq.bar0_addr,
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(unsigned long long)acq.bar1_addr,
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(unsigned long long)acq.bar3_addr);
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/* Verify BARs via config space (setpci) while die is acquired */
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printf("\nConfig space verification:\n");
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{
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char cmd[256], line[128];
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FILE *pp;
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/* Read BAR 0 (reg 0x10), BAR 1 lo (0x14), BAR 1 hi (0x18) */
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snprintf(cmd, sizeof(cmd),
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"setpci -s 07:00.0 0x10.L 0x14.L 0x18.L 0x1C.L 0x20.L 0x04.W");
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pp = popen(cmd, "r");
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if (pp) {
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int reg_idx = 0;
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const char *names[] = {"BAR0", "BAR1_lo", "BAR1_hi", "BAR3_lo", "BAR3_hi", "CMD"};
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while (fgets(line, sizeof(line), pp) && reg_idx < 6) {
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line[strcspn(line, "\n")] = '\0';
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printf(" %s = 0x%s\n", names[reg_idx], line);
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reg_idx++;
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}
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pclose(pp);
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}
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/* Also check downstream bridge 06:08.0 memory windows */
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printf("\nBridge 06:08.0 windows:\n");
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snprintf(cmd, sizeof(cmd),
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"setpci -s 06:08.0 0x20.W 0x22.W 0x24.W 0x26.W 0x28.L 0x2C.L 0x04.W");
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pp = popen(cmd, "r");
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if (pp) {
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int reg_idx = 0;
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const char *names[] = {"MEM_BASE", "MEM_LIMIT", "PREF_BASE", "PREF_LIMIT",
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"PREF_BASE_HI", "PREF_LIMIT_HI", "CMD"};
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while (fgets(line, sizeof(line), pp) && reg_idx < 7) {
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line[strcspn(line, "\n")] = '\0';
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printf(" %s = 0x%s\n", names[reg_idx], line);
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reg_idx++;
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}
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pclose(pp);
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}
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}
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/* Map BAR 0 via /dev/mem (first 4 KB page) */
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mem_fd = open("/dev/mem", O_RDONLY | O_SYNC);
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if (mem_fd < 0) {
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perror("open /dev/mem");
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goto release;
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}
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mapped = mmap(NULL, 4096, PROT_READ, MAP_SHARED, mem_fd, acq.bar0_addr);
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if (mapped == MAP_FAILED) {
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perror("mmap BAR 0");
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close(mem_fd);
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goto release;
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}
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reg = (volatile uint32_t *)mapped;
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/* NV_PMC_BOOT_0 at offset 0x0 — GPU identification register */
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boot0 = reg[0];
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/* NV_PMC_BOOT_42 at offset 0x0 is actually PMC_BOOT_0.
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* Also read offset 0x4 (PMC_INTR) for another data point */
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pmc_id = reg[1];
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printf("BAR0[0x00] (NV_PMC_BOOT_0) = 0x%08x\n", boot0);
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printf("BAR0[0x04] = 0x%08x\n", pmc_id);
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if (boot0 == 0xFFFFFFFF) {
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printf("\n** DIE IS UNREACHABLE (fallen off bus) **\n");
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} else {
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printf("\nDie responds! Implementation ID: 0x%02x, Chip: 0x%03x\n",
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(boot0 >> 20) & 0xFF, (boot0 >> 0) & 0xFFF);
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}
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/* Read a few more offsets for diagnostics */
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printf("\nFirst 16 registers:\n");
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for (int i = 0; i < 16; i++)
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printf(" [0x%02x] = 0x%08x\n", i * 4, reg[i]);
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munmap(mapped, 4096);
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close(mem_fd);
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release:
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memset(&rel, 0, sizeof(rel));
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rel.die_id = die_id;
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ioctl(fd, BAR_SWAP_RELEASE, &rel);
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close(fd);
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printf("\nDie %d released.\n", die_id);
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return (boot0 == 0xFFFFFFFF) ? 1 : 0;
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}
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