106 lines
4.2 KiB
C
106 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only OR AGPL-3.0-or-later
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/*
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* k80-strap-quirk.c — make all 16 GK210 dies of an 8x K80 machine map at 256 MB at
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* boot on the BTC-S37, fully in-kernel, with zero userspace. Two cooperating parts:
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*
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* 1. quirk_gk210_shrink_bar1 (DECLARE_PCI_FIXUP_HEADER)
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* Shrinks the kernel's *view* of each die's BAR1 to 256 MB BEFORE bus
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* resource assignment. Default BAR1 = 16 GB; 16 dies x 16 GB = 256 GB can't
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* fit under this board's 36-bit (64 GB) ceiling, so the kernel's allocator
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* fails to place it and DISABLES the bridge prefetchable window — which
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* strands the last card ("card 8": dies 20/21 on root port 1c.7) and makes
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* its dies stop decoding entirely. By pre-shrinking the resource to 256 MB
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* the allocator never attempts the 16 GB placement, never disables any
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* bridge, and assigns all 16 dies a 256 MB BAR1 with every bridge window
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* alive. Modeled on quirk_s3_64M (drivers/pci/quirks.c).
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*
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* Must be a HEADER fixup, NOT EARLY: pci_fixup_early runs before
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* pci_read_bases() (BAR0/resource[] not populated -> the EARLY version
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* reported "BAR0 unassigned, skipping"). pci_fixup_header runs after sizing
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* but before assignment (verified against drivers/pci/probe.c).
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*
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* 2. k80_strap_silicon (late_initcall)
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* The HEADER fixup only changes the kernel's VIEW; the silicon still decodes
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* a 16 GB aperture. Because the two dies on a card share one bridge window,
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* an unstrapped 16 GB die would alias over its sibling's region. So after PCI
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* resources are assigned (when BAR0 is reachable), write each die's PSTRAPS
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* (BAR0 + 0x101000, field [17:14] = 2 = 256 MB, override bit 31) so the
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* silicon decode matches its 256 MB assignment. The HEADER fixup is what
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* keeps every bridge alive so this can reach all 16 — card 8 included.
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*
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* Result: drop this kernel in, reboot, all 16 dies map at 256 MB. No barswap, no
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* runtime tool, no VBIOS flash, no userspace. (PSTRAPS mechanism proven on these
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* exact dies at runtime before being baked in.)
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*/
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#define GK210_DEVICE_ID 0x102d
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#define GK210_BAR1_256MB 0x10000000UL /* 256 MB */
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#define GK210_PSTRAPS 0x101000u
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#define GK210_BAR1_SHIFT 14
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#define GK210_BAR1_MASK (0xfu << GK210_BAR1_SHIFT)
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#define GK210_BAR1_VAL_256 (2u << GK210_BAR1_SHIFT) /* ladder: 2 = 256 MB */
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#define GK210_OVERRIDE_EN (1u << 31)
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/* Part 1: shrink the kernel's BAR1 resource before assignment. */
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static void quirk_gk210_shrink_bar1(struct pci_dev *dev)
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{
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struct resource *r = &dev->resource[1]; /* BAR1: 64-bit prefetchable */
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if (!(r->flags & IORESOURCE_MEM))
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return;
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if (resource_size(r) <= GK210_BAR1_256MB)
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return; /* already small (e.g. a rescan) */
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pci_info(dev, "k80_strap: BAR1 %lluMB -> 256MB (resource shrink before assignment)\n",
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(unsigned long long)(resource_size(r) >> 20));
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r->flags |= IORESOURCE_UNSET;
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r->start = 0;
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r->end = GK210_BAR1_256MB - 1;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, GK210_DEVICE_ID,
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quirk_gk210_shrink_bar1);
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/* Part 2: after assignment, strap the silicon BAR1 to 256 MB so the hardware
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* decode matches the kernel's 256 MB assignment (no intra-card aliasing). */
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static int __init k80_strap_silicon(void)
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{
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struct pci_dev *dev = NULL;
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while ((dev = pci_get_device(PCI_VENDOR_ID_NVIDIA, GK210_DEVICE_ID, dev))) {
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resource_size_t bar0 = pci_resource_start(dev, 0);
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void __iomem *base;
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u16 cmd;
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u32 v;
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if (!bar0)
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continue;
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/* BAR0 must decode for the PSTRAPS write to land. */
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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if (!(cmd & PCI_COMMAND_MEMORY))
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pci_write_config_word(dev, PCI_COMMAND,
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cmd | PCI_COMMAND_MEMORY);
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base = ioremap(bar0 + GK210_PSTRAPS, 8);
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if (!base)
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continue;
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v = readl(base);
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if (v != 0xffffffffu) { /* reachable */
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v = (v & ~GK210_BAR1_MASK) | GK210_BAR1_VAL_256 | GK210_OVERRIDE_EN;
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writel(v, base);
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(void)readl(base); /* post-write read barrier */
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pci_info(dev, "k80_strap: silicon BAR1 -> 256MB (PSTRAPS=0x%08x)\n", v);
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} else {
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pci_info(dev, "k80_strap: silicon unreachable, skipping\n");
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}
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iounmap(base);
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}
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return 0;
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}
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late_initcall(k80_strap_silicon);
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