194 lines
10 KiB
C
194 lines
10 KiB
C
/* SPDX-License-Identifier: AGPL-3.0-or-later */
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/* Copyright (C) 2026 David (Corey) Herrera */
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/**
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* @file ft_tt_dram_stripe.h
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* @brief Which DOOR of a DRAM bank each concurrent reader uses — the port/row rotation that
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* turns one saturated endpoint into several, with no data moved and no kernel change.
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*
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* ---------------------------------------------------------------------------
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* THE STRUCTURAL FACT THIS MODULE EXISTS FOR
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* ---------------------------------------------------------------------------
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* A Blackhole GDDR bank exposes THREE NoC ports, and they are **three doors into ONE memory,
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* not three memories** (ft_tt_coord.h; the west/east split is
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* ft_tt_arch_blackhole.c:93). The same byte at the same DRAM address is reachable through
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* port 0, 1 or 2. **So choosing a port moves no data.** It is purely a choice of endpoint
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* coordinate, which makes it the cheapest bandwidth lever in the backend: an addressing
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* change, host-side, that no kernel and no weight layout can see.
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*
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* ---------------------------------------------------------------------------
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* THE THREE CEILINGS, MEASURED 2026-08-14 (plan Phase 6.7)
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* ---------------------------------------------------------------------------
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* ENDPOINT ~45 GB/s one (bank, port) pair, however many readers aim at it. NoC-side
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* NoC ROW ~60 GB/s SHARED by every endpoint on one NoC y. Two endpoints in one COLUMN
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* do not interact at all; two on one ROW share this
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* BANK ~64 GB/s the memory itself. Two ports of one bank already reach 58.5 of it,
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* so the third door buys little per bank and a lot per card
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* CARD 502 GB/s 8 x 63.9, with no room left for a NoC term at the card level
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*
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* A reader set aimed at ONE port of a bank is therefore capped at ~45 GB/s while the bank
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* behind it can serve ~64. Rotating the port across the readers lifts the cap to the bank's
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* own limit. Doing the same across all 8 banks measured **216 -> 296.8 GB/s, +33%, for free**
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* — because a single port INDEX occupies only 4 of the 12 NoC rows (port p of bank b and of
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* bank b+4 share a y), and rotating spreads the traffic over distinct rows.
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*
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* ---------------------------------------------------------------------------
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* WHAT THIS MODULE IS NOT
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* ---------------------------------------------------------------------------
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* It does not stripe an operand across BANKS. That requires the bytes to actually live in
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* more than one bank, so it is a placement decision a LOADER makes — `ft_tt_dram_shard.h`,
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* which calls this module for the doors once it has decided the banks. The rotation here
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* raises a per-operand ceiling from one endpoint (~45) to one bank (~64); bank striping is
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* what raises it past that.
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*
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* ---------------------------------------------------------------------------
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* THE LADDER'S FIRST TWO RUNGS, MEASURED IN ISOLATION 2026-08-15
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* ---------------------------------------------------------------------------
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* N Tensix cores reading the SAME 96 KiB block from the SAME bank at the SAME address, the
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* arms differing only in which door each reader was handed (tests/test_multicast_bench.c):
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*
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* N 1 2 3 4 aggregate
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* one door 3092 4442 6662 8882 ns 44.3 GB/s from N=2 up
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* rotated 3092 3625 4622 6191 ns 63.5-63.8 GB/s from N=3 up
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*
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* The un-rotated arm is pinned at the ENDPOINT ceiling however many cores it has; the rotated
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* arm reaches 99.4% of the BANK's own measured 63.9. N=1 is byte-identical in both, which is
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* the control that this is addressing and nothing else.
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*
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* @status Off-hardware in tests/test_cooperative_matmul_plan.c; MEASURED on the card through
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* ft_tt_op_matmul_cooperative.h by tests/test_cooperative_matmul.c, and in isolation by
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* tests/test_multicast_bench.c.
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* @issues None
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* @todo None
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*/
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#ifndef FT_TT_DRAM_STRIPE_H
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#define FT_TT_DRAM_STRIPE_H
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#include <stdint.h>
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#include "ft_tt_coord.h"
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/** Storage capacity for the doors of one bank — NOT a statement about any part. Blackhole
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* has 3 (ft_tt_arch_blackhole.c). ft_tt_dram_port_set_build() refuses a grid whose
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* architecture declares more, naming both numbers, rather than overflowing the array. */
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#define FT_TT_DRAM_STRIPE_MAX_PORTS 4u
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/** One door into one bank. */
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typedef struct ft_tt_dram_endpoint {
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uint32_t logical_bank;
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uint32_t port;
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/** In the coordinate system the set was built for. TRANSLATED is what a transfer is
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* AIMED with; this is the value that reaches a runtime-arg block. */
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ft_tt_noc_coord coord;
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/**
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* NoC 0 y — the row whose ~60 GB/s two endpoints SHARE.
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*
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* Carried separately and always in NOC 0, because the row limit is a property of the
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* physical node and the translated grid is an alias with its own y. Reading a row off a
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* translated coordinate would be reading the alias, not the wire.
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*/
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uint32_t noc_row;
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} ft_tt_dram_endpoint;
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/** Every door of one bank, in port order. */
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typedef struct ft_tt_dram_port_set {
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uint32_t logical_bank;
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uint32_t port_count;
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ft_tt_dram_endpoint port[FT_TT_DRAM_STRIPE_MAX_PORTS];
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} ft_tt_dram_port_set;
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/**
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* Resolve every NoC port of one DRAM bank, from LIVE telemetry.
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*
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* Both coordinate systems are asked for per port: `coord` in `system` (what a transfer is
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* aimed with) and `noc_row` always in NOC 0 (what the row-sharing rule is expressed in).
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* Nothing here is probed or hardcoded — a wrong DRAM endpoint does not fail a read, it hangs
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* the chip (DEV_NOTES.md §1).
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*
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* @param grid topology from ARC telemetry
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* @param logical_bank 0 .. ft_tt_coord_dram_bank_count()-1
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* @param system the space `coord` is wanted in; usually FT_TT_COORD_TRANSLATED
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* @param out written only on success
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* @return FT_TT_OK; FT_TT_EINVAL on a NULL argument or a bank out of range;
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* FT_TT_ENOMEM if the architecture declares more ports than this module can hold;
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* otherwise as ft_tt_coord_dram_port(). Every reason is logged
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*
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* Thread-safe: yes Reentrant: yes Signal-safe: no (logs on failure)
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*/
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int ft_tt_dram_port_set_build(const ft_tt_grid_info *grid, uint32_t logical_bank,
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ft_tt_coord_system system, ft_tt_dram_port_set *out);
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/**
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* The door reader `reader_index` of a concurrent group should use: `reader_index % port_count`.
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*
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* Round-robin rather than anything cleverer, because the measured rule is BALANCE: the
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* outstanding-read budget is per endpoint, and an unbalanced map cost 30% and was worse than
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* either neighbouring balanced reader count (plan Phase 6.7). Modulo is the assignment that
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* differs by at most one reader between doors for every group size.
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*
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* @return the endpoint, or NULL if `set` is NULL or empty
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*
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* Thread-safe: yes Reentrant: yes Signal-safe: yes
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*/
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const ft_tt_dram_endpoint *ft_tt_dram_port_set_reader_endpoint(const ft_tt_dram_port_set *set,
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uint32_t reader_index);
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/**
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* How many pairs of the given endpoints sit on ONE NoC row — the measured ~60 GB/s two
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* endpoints share where two in one column do not interact at all.
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*
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* DISTINCT endpoints only: the same (bank, port) appearing twice is one endpoint used by two
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* readers, which is the normal case and not a collision.
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*
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* This is a PERFORMANCE fact, not a correctness one — a colliding pair returns the right
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* bytes, slowly — so it is reported rather than refused, and the caller decides. Anything
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* that plans concurrent traffic should check it and say so in its own report.
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*
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* @param endpoints the endpoints in concurrent use
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* @param count how many
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* @param out_first_left may be NULL; index of the first colliding pair's first member
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* @param out_first_right may be NULL; and its second
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* @return the number of colliding DISTINCT pairs; 0 on a NULL/empty array
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*
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* Thread-safe: yes Reentrant: yes Signal-safe: yes
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*/
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uint32_t ft_tt_dram_stripe_shared_rows(const ft_tt_dram_endpoint *endpoints, uint32_t count,
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uint32_t *out_first_left, uint32_t *out_first_right);
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/**
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* Choose a DOOR for each reader whose BANK is already decided by where its bytes live.
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*
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* This is the assignment problem the two measured striping rules pose together, and neither
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* can be satisfied by a formula:
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*
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* ROWS two endpoints on one NoC y share ~60 GB/s, and port p of bank b and of bank b+4
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* ARE one row — so `port = reader % 3` collides as soon as the bank list contains
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* a b and a b+4, which any list of more than four banks does.
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* BALANCE the outstanding-read budget is per endpoint, and an unbalanced map measured 30%
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* worse than either neighbouring balanced core count.
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*
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* Greedy in reader order, deterministic: each reader takes the door of its own bank that adds
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* the least contention, and the cost order is the LADDER's, not the intuitive one — a fresh
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* door on a used ROW beats a used DOOR on a fresh row, because two streams through one
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* endpoint share ~45 GB/s where two endpoints of one row share ~60.
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*
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* Row collisions are therefore expected, not a failure: this part has 24 DRAM endpoints on
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* only 12 rows, so any assignment of more than 12 concurrent streams MUST double up. The
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* caller checks with ft_tt_dram_stripe_shared_rows() and says what it found.
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*
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* @param grid topology from ARC telemetry
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* @param banks `count` logical bank indices, one per reader, in reader order
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* @param count readers; 0 is refused
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* @param system the space `coord` is wanted in; usually FT_TT_COORD_TRANSLATED
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* @param out `count` endpoints, written only on success
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* @return FT_TT_OK; FT_TT_EINVAL on a NULL argument or a zero count; otherwise as
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* ft_tt_dram_port_set_build()
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*
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* Thread-safe: yes Reentrant: yes Signal-safe: no (logs on failure)
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*/
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int ft_tt_dram_stripe_choose_ports(const ft_tt_grid_info *grid, const uint32_t *banks,
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uint32_t count, ft_tt_coord_system system,
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ft_tt_dram_endpoint *out);
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#endif /* FT_TT_DRAM_STRIPE_H */
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