256 lines
12 KiB
C
256 lines
12 KiB
C
/* SPDX-License-Identifier: AGPL-3.0-or-later */
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/**
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* @file ft_tt_arch_blackhole.c
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* @brief The Blackhole (p100 / p150) architecture table.
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*
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* Every hardware fact below names where it came from. "Docs" means the public
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* tt-isa-documentation tree (paths relative to its root):
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* [COORD] BlackholeA0/NoC/Coordinates.md — coordinate translation table and
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* the harvested-tile placement rules
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* [LUA] Diagrams/Src/NoC.lua — machine-readable tile map: NocSize_Arch.bh,
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* TileLabel_BH (what sits at each NoC #0 node), and the bh_y1223 /
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* bh_y25 / bh_x8 translated-numbering examples
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* [BH] BlackholeA0/README.md — tile counts per product
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* [TLB] BlackholeA0/PCIExpressTile/HostToDeviceTLBs.md
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* [RESET] BlackholeA0/TensixTile/SoftReset.md
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* [RISCV] BlackholeA0/TensixTile/BabyRISCV/README.md (memory map)
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* [TILE] BlackholeA0/TensixTile/README.md
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* [ETHDMP] BlackholeA0/EthernetTile/Samples/ethdump/ethdump.c (PCI ids)
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* Values no public page states are marked TEST (asserted by a named oracle
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* test) or HEADER (the compiled Foundry header the header gate compares it to,
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* so test_arch's "headers agree" case pins it).
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*
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* @status Complete for every field a Foundry caller reads. tile_height,
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* tile_width and faces_per_tile are 0: no public page states them and no
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* caller reads them.
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* @issues None
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* @todo None
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*/
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#include "ft_tt_arch.h"
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#include <stddef.h>
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#include <stdint.h>
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#include "ft_tt_kmd.h"
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/* ------------------------------------------------------------------------- */
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/* Identity */
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/* ------------------------------------------------------------------------- */
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/* [ETHDMP] PCI_VENDOR_ID_TENSTORRENT 0x1E52, PCI_DEVICE_ID_BLACKHOLE 0xB140. */
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#define BLACKHOLE_PCI_VENDOR_ID 0x1E52u
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static const uint16_t blackhole_pci_device_ids[] = { 0xB140u };
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/* ------------------------------------------------------------------------- */
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/* Tensix */
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/* ------------------------------------------------------------------------- */
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/* [LUA] TileLabel_BH: every node with x not in {0, 8, 9} and y >= 2 is a Tensix
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* ("T"). [COORD] table: Tensix at x 1-7 and 10-16, y 2-11 — 14 x 10 = 140, which
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* [BH] confirms. x = 8 is the ARC/security/CPU column, x = 0 and 9 are DRAM. */
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static const uint8_t blackhole_tensix_noc_x[14] = { 1, 2, 3, 4, 5, 6, 7,
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10, 11, 12, 13, 14, 15, 16 };
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static const uint8_t blackhole_tensix_noc_y[10] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 };
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/* TEST (tests/test_coord.c harvest_bit_table, tests/test_harvesting.c
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* layout_telemetry_bit_by_column): ARC reports enabled columns outside-in,
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* alternating west then east, so grid column 13 (x = 16) is telemetry bit 1. No
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* public page documents the telemetry encoding; this card reports all 14 bits
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* set, so the order cannot be observed here either. */
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static const uint8_t blackhole_tensix_telemetry_bit[14] = { 0, 2, 4, 6, 8, 10, 12,
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13, 11, 9, 7, 5, 3, 1 };
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/* ------------------------------------------------------------------------- */
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/* DRAM */
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/* ------------------------------------------------------------------------- */
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/* [LUA] TileLabel_BH: DRAM columns x = 0 (D0-D3) and x = 9 (D4-D7); by y the
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* bank is {0,0,1,1,2,3,3,3,2,2,1,0} for y = 0..11, so each bank has 3 tiles
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* ([BH]: 24 DRAM tiles, "each 4 GiB is exposed identically on 3 tiles").
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* Port order within a bank is the order of the translated y each tile receives
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* in the bh_y1223 example (y0->12, y1->13, y11->14, y2->15, y10->16, y3->17,
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* y9->21, y4->22, y8->23, y5->18, y7->19, y6->20), i.e. bank-relative. */
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static const ft_tt_arch_xy blackhole_dram_noc0[8 * 3] = {
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{ 0, 0 }, { 0, 1 }, { 0, 11 }, /* bank 0 */
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{ 0, 2 }, { 0, 10 }, { 0, 3 }, /* bank 1 */
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{ 0, 9 }, { 0, 4 }, { 0, 8 }, /* bank 2 */
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{ 0, 5 }, { 0, 7 }, { 0, 6 }, /* bank 3 */
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{ 9, 0 }, { 9, 1 }, { 9, 11 }, /* bank 4 */
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{ 9, 2 }, { 9, 10 }, { 9, 3 }, /* bank 5 */
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{ 9, 9 }, { 9, 4 }, { 9, 8 }, /* bank 6 */
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{ 9, 5 }, { 9, 7 }, { 9, 6 }, /* bank 7 */
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};
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/* ------------------------------------------------------------------------- */
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/* Ethernet */
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/* ------------------------------------------------------------------------- */
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/* [LUA] TileLabel_BH, y == 1 row: E0 at x 1, E2 x 2, ... E12 x 7, E13 x 10,
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* E11 x 11, ... E1 x 16. Indexed by channel number here. */
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static const ft_tt_arch_xy blackhole_eth_noc0[14] = {
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{ 1, 1 }, { 16, 1 }, { 2, 1 }, { 15, 1 }, { 3, 1 }, { 14, 1 }, { 4, 1 },
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{ 13, 1 }, { 5, 1 }, { 12, 1 }, { 6, 1 }, { 11, 1 }, { 7, 1 }, { 10, 1 },
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};
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/* ------------------------------------------------------------------------- */
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/* Fixed blocks */
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/* ------------------------------------------------------------------------- */
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/* [LUA] TileLabel_BH, y == 0 row: "PCIe 0" at x 2, "PCIe 1" at x 11. [BH]: 2 tiles. */
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static const ft_tt_arch_xy blackhole_pcie_noc0[2] = { { 2, 0 }, { 11, 0 } };
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/* [LUA] TileLabel_BH, x == 8 column: CPU 0-3 at y 3, CPU 8-11 at y 5, CPU 12-15
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* at y 7, CPU 4-7 at y 9. Logical order here is by y. */
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static const ft_tt_arch_xy blackhole_l2cpu_noc0[4] = { { 8, 3 }, { 8, 5 }, { 8, 7 }, { 8, 9 } };
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/* TEST (tests/test_coord.c test_l2cpu_bit_order): telemetry bit 0 -> (8,3),
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* 1 -> (8,9), 2 -> (8,5), 3 -> (8,7). Consistent with the docs: it is the cluster
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* number implied by the CPU ranges above ([LUA] TileLabel_BH), and the [LUA]
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* bh_x8 example gives exactly those tiles translated y 26, 27, 28, 29. */
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static const uint8_t blackhole_l2cpu_telemetry_bit[4] = { 0, 2, 3, 1 };
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/* [LUA] TileLabel_BH: the empty ("") labels are NoC nodes with no endpoint tile —
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* twelve in row 0 (x 1-7 and 10-16 minus the two PCIe tiles), (8,1), and
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* (8,4), (8,6), (8,8), (8,10), (8,11) in the CPU column. 18 in all. */
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static const ft_tt_arch_xy blackhole_router_noc0[18] = {
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{ 1, 0 }, { 3, 0 }, { 4, 0 }, { 5, 0 }, { 6, 0 }, { 7, 0 },
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{ 10, 0 }, { 12, 0 }, { 13, 0 }, { 14, 0 }, { 15, 0 }, { 16, 0 },
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{ 8, 1 }, { 8, 4 }, { 8, 6 }, { 8, 8 }, { 8, 10 }, { 8, 11 },
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};
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/* ------------------------------------------------------------------------- */
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/* The table */
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/* ------------------------------------------------------------------------- */
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static const ft_tt_arch blackhole_arch = {
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.id = FT_TT_ARCH_BLACKHOLE,
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.name = "Blackhole",
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.pci_vendor_id = BLACKHOLE_PCI_VENDOR_ID,
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.pci_device_ids = blackhole_pci_device_ids,
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.pci_device_id_count = 1u,
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/* HEADER: ft_tt_kmd.h's chip_arch value for Blackhole. */
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.kmd_chip_arch = (uint64_t)FT_TT_KMD_ARCH_BLACKHOLE,
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/* [LUA] NocSize_Arch.bh = { w = 17, h = 12 }. */
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.noc = { .size_x = 17u, .size_y = 12u },
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.tensix = {
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.column_count = 14u,
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.row_count = 10u,
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/* [COORD] "If any Tensix columns are fused off ... X is remapped to put
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* the fused columns at maximal X" — Blackhole harvests columns. */
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.harvest_axis = FT_TT_HARVEST_AXIS_COLUMN,
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.noc_x_by_column = blackhole_tensix_noc_x,
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.noc_y_by_row = blackhole_tensix_noc_y,
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.telemetry_bit_by_column = blackhole_tensix_telemetry_bit,
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},
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.dram = {
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.bank_count = 8u,
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.ports_per_bank = 3u,
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/* [BH] p100 exposes 28 of 32 GiB: at most one 4 GiB bank is fused off. */
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.max_harvested_banks = 1u,
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.noc0 = blackhole_dram_noc0,
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/* [COORD] table: DRAM aliases at x 17-18, y 12-23, 3 y per bank. Which
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* physical column lands on x = 17 for an UNHARVESTED part is TEST
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* (tests/test_coord.c test_dram_full_grid: banks 0-3 at 17). */
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.translated_origin_x = 17u,
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.translated_origin_y = 12u,
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.translated_column_count = 2u,
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},
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.eth = {
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.channel_count = 14u, /* [BH] 14 Ethernet tiles on the full ASIC. */
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.noc0 = blackhole_eth_noc0,
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/* [COORD] table: Ethernet aliases at x 20-31, y 25; [LUA] bh_y25 packs
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* the enabled channels there in channel order. */
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.translated_origin_x = 20u,
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.translated_origin_y = 25u,
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},
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.fixed = {
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.arc = { 8u, 0u }, /* [LUA] TileLabel_BH x 8, y 0 "ARC". */
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.security = { 8u, 2u }, /* [LUA] TileLabel_BH x 8, y 2 "SEC". */
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.security_count = 1u, /* [BH] */
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.pcie_count = 2u,
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.pcie_noc0 = blackhole_pcie_noc0,
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.pcie_translated = { 19u, 24u }, /* [COORD] "19, 24: PCI Express tile". */
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.l2cpu_count = 4u, /* [BH] */
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.l2cpu_noc0 = blackhole_l2cpu_noc0,
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.l2cpu_telemetry_bit_by_tile = blackhole_l2cpu_telemetry_bit,
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.router_count = 18u,
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.router_noc0 = blackhole_router_noc0,
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},
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/* [TLB]: 210 windows — 0-201 are 2 MiB (201 reserved for the kernel driver),
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* 202-209 are 4 GiB; config at BAR0 0x1FC0_0000 as 210 x 12-byte entries
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* followed by 32 strided words: 210 * 12 + 32 * 4 = 0xA58 bytes. */
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.tlb = {
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.window_2m_count = 202u,
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.window_4g_count = 8u,
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.kernel_window_index = 201u,
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.register_stride_bytes = 12u,
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.registers_offset = 0x1FC00000u,
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.registers_length = 0xA58u,
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.strided_window_count = 32u,
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},
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/* No public page documents Blackhole ARC telemetry. Each value is what
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* Foundry's card-verified ARC paths use: the reset-unit scratch registers at
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* 0x80030400 with the table pointer in scratch 13 and the values pointer in
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* scratch 12, and the CSM window 0x1000_0000 + 512 KiB (ft_tt_udrv_arc_msg.h,
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* driven on the card by tests/test_udrv_card_arc.c and
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* tests/test_udrv_rehearsal.c; CSM base also in
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* tests/test_phase1b_telemetry.c). Grid tags 34 (Tensix columns),
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* 36 (GDDR), 37 (L2CPU), 40 (NoC translation) are named by tests/test_coord.c;
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* 35 (Ethernet) is the one tag no oracle names — see the report. */
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.telemetry = {
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.scratch_base = 0x80030400u,
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.table_pointer_scratch_index = 13u,
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.values_pointer_scratch_index = 12u,
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.csm_base = 0x10000000u,
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.csm_size = 0x80000u,
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.tag_enabled_tensix_col = 34u,
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.tag_enabled_eth = 35u,
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.tag_enabled_gddr = 36u,
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.tag_enabled_l2cpu = 37u,
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.tag_noc_translation = 40u,
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},
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.core = {
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.processor_count = 5u, /* [TILE] "5x Baby RISCV cores". */
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/* [RISCV] memory map has no NCRISC IRAM row on Blackhole. */
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.has_ncrisc_iram = false,
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/* HEADER (ft_tt_mailbox.h): the firmware-interface contract. */
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.programmable_core_type_count = 4u,
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.max_num_kernels = 3u,
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.subordinate_map_size = 4u,
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.processors_for_threading_variables = 0u,
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.circular_buffer_count = 64u,
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.l1_size = 1536u * 1024u, /* [TILE] "1536 KiB of RAM called L1". */
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.l1_alignment = 16u, /* HEADER (ft_tt_memmap.h) */
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.dram_alignment = 64u, /* HEADER (ft_tt_memmap.h) */
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/* HEADER (ft_tt_memmap.h): the usable span of each bank. [BH] gives 4 GiB
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* per bank physically; the compiled map stops 16 MiB short of that. */
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.dram_bytes_per_bank = 0xFF000000u,
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.mailbox_base = 96u, /* HEADER (ft_tt_memmap.h) */
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.soft_reset_address = 0xFFB121B0u, /* [RESET] RISCV_DEBUG_REG_SOFT_RESET_0 */
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/* [RESET] bits 11 (B), 12-14 (T0-T2), 18 (NC). */
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.soft_reset_all_riscs_mask = (1u << 11) | (1u << 12) | (1u << 13) | (1u << 14) |
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(1u << 18),
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.noc_overlay_base = 0xFFB40000u, /* [RISCV] NOC_OVERLAY_START_ADDR */
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.noc_stream_register_span = 0x1000u, /* HEADER (ft_tt_memmap.h) */
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.tile_height = 0u,
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.tile_width = 0u,
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.faces_per_tile = 0u,
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},
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};
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const ft_tt_arch *ft_tt_arch_blackhole(void)
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{
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return &blackhole_arch;
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}
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